1. Field of the Invention
This invention relates to socketless separable connectors for chip carriers for semiconductor chips for providing the shortest possible path between pads on the printed circuit board and the leads on the chip carrier.
2. Description of the Prior Art
Semiconductor chips, such as integrated circuits, are normally mounted on chip carriers as is well known in the prior art. These chip carriers include ceramic elements or other insulating material upon which the chips are mounted, with lead frames extending from pads on the chips to the exterior of the chip carrier for interconnection with elements or the outside world such as, for example, printed circuit boards. The prior art chip carriers have functioned very satisfactorily for their intended purpose in the past. However, the speed of operation of the circuits has increased and continues to increase. Since the chip carriers themselves are normally formed of ceramic materials and the like which are good dielectrics, the semiconductor packages have built-in capacitance and self-inductance in the leads required for the bonding pads on the chips for connection to the external world. These capacitances and inductances are a function of frequency and increase as the speed of operation increases. The increase in system inductance and capacitance decreases the speed at which the circuits are capable operating. These capactances and inductances also appear in the sockets which connect the packages to integrated circuit boards and the like. It is desirable to increase the operating speed of electronic components and, for this reason, it is necessary to decrease the bulit-in capacitance and self-inductance in the semiconductor chip package as well as the sockets therefore.
It is known that, the longer the leads, the greater will be the built-in capacitance and self-inductance. It is therefore the desire to provide a connection between the leads on a chip carrier and the pads of an associated printed circuit board which are as short as possible with elimination of sockets to minimize inductive and capacitive properties when making connection to a pad on a printed circuit board or the like from a lead on a semiconductor chip carrier.